Join Accellera at DVCon U.S. 2025

We hope to see you during DVCon U.S. February 24-27 in San Jose, California where we’ll have five informative workshops presented by our working group leaders. We’ll also have a luncheon presentation featuring the latest Accellera updates, the presentation of the prestigious Technical Excellence Award, and an overview of our newest standard.

The following Accellera-sponsored DVCon events are open to registered DVCon attendees (these events are not part of the free registration option).

IEEE 1801-2024 Workshop

“Introduction of IEEE 1801-2024 (UPF 4.0)”

Monday, February 24
9:00-10:30am

This workshop will explore the key advancements in the IEEE 1801-2024 (UPF 4.0) standard, designed to address the growing complexity of modern low-power architectures. Attendees will gain insights into the new methodologies for verification, implementation, and reuse of power intent specifications that are critical for flexible IP design, analog-digital interfaces, and state retention modeling.

Universal Verification Methodology (UVM) Workshop

“Moving Forward with IEEE 1800.2 UVM: Practical Insights and the Benefits of Migration”

Monday, February 24
11:00-12:30pm

This workshop highlights the latest enhancements in the IEEE 1800.2 UVM standard, as introduced in Accellera's reference implementation (2020.3.1). It offers practical guidance for verification engineers, focusing on performance improvements, functional updates, and strategies for a smooth migration from UVM 1.2.

Accellera Luncheon

Join Accellera for Lunch!

Monday, February 24
12:30-1:30

Accellera Update and Look to the Future presented by Lu Dai, Accellera Chair
Accellera Technical Excellence Award Presentation
Introduction to the UVM-MS 1.0 standard

Portable Stimulus Workshop

“PSS Comes of Age: Runtime Behavioral Coverage, Methodology, and More”

Monday, February 24
3:30-5:00

This workshop will dive into the key advancements in the Portable Stimulus Standard (PSS) 3.0 and ongoing efforts by the working group, highlighting the language's evolution and maturity. Attendees will gain a deeper understanding of PSS 3.0’s capabilities and the tools available to streamline portable stimulus test creation and implementation.

IP-XACT Workshop

“SoC Development Automation using the IP-XACT 1685-2022 Standard”

Thursday, February 27
9:00-10:30

This workshop explores the complexities of the SoC development process and highlights how the IEEE IP-XACT 1685-2022 standard streamlines workflows, fosters standardization, and enables automation. Attendees will gain insights into optimizing SoC development by standardizing processes and integrating automation with IP-XACT.

Clock Domain Crossing (CDC) Workshop

“CDC/RDC Interchange Format Standard”

Thursday, February 27
11:00-12:30

This workshop highlights the critical role of Clock Domain Crossing and Reset Domain Crossing (RDC) analysis in modern SoC development, addressing challenges posed by increasing design complexity and diverse verification tool ecosystems. Attendees will learn how standardization can enhance quality and efficiency in CDC-RDC analysis for advanced SoC designs.

For a complete program schedule, including exhibition hours and registration information, visit the DVCon U.S. 2025 website.