Community Newsletter: July 2026

IN THIS ISSUE:

• Message from the Chair: A Strong First Half of 2026!
• Recent Press Coverage
  • SemiWiki: “Accellera Updates at DVCon U.S.”
• Functional Safety Language Standard Public Review Coming Next Week
• Join Accellera at the 63rd Design Automation Conference
  • Luncheon Panel Focused on “Embracing AI for Advanced Design and Verification”
• Upcoming Events
  • Submit your proposals for DVCon U.S. 2027
  • DVCon India
  • DVCon Japan
  • DVCon Europe
  • SystemC Evolution Day
• New Videos Available!
  • Learning Portable Stimulus Video Series
  • SystemC Fika Videos
• More Resources
  • DVCon Archives from Around the Globe
  • Hundreds of Videos Available On-Demand on Accellera’s YouTube Channel
  • IEEE Program – Download Standards Fee Free

 

Message from the Chair

As we head into the second half of 2026, I'm pleased to share that Accellera continues to make excellent progress across our conferences, standards development, and educational initiatives. The strength of our community has never been more evident, and I'd like to thank our members, volunteers, and industry partners for their continued commitment to advancing electronic design automation standards.

This spring's DVCon U.S. was our most successful conference to date, setting an all-time attendance record and welcoming many new exhibitors to our new venue in Santa Clara. The energy throughout the event was exceptional, with engaging technical discussions, including many focused on the growing role of AI in EDA, as well as our first Accellera-sponsored attendee reception, which provided another opportunity for the community to connect. We're also excited by the continued momentum of DVCon China, which has received outstanding sponsor support and has firmly established itself as one of the premier technical conferences for design and verification professionals in the region.

Our standards activities remain equally strong. Work continues to advance across multiple working groups, with the Functional Safety Language (FSL) draft standard available for public review next week and releases for UVM 3.2 and SystemVerilog Mixed-Signal Interface (SV-MSI) on the horizon. The SystemC AMS standard will soon be submitted to IEEE, broadening its global reach. These milestones reflect the tremendous dedication of our working group members.

Education remains another important priority. We've recently introduced the first three parts of our new "Learning PSS" video series, providing an excellent introduction to the Portable Stimulus Standard for both new and experienced users.

Looking ahead, we're preparing for another exciting Design Automation Conference in Long Beach later this month. I hope you'll join us for the Accellera-sponsored luncheon on Tuesday, July 28, where an outstanding panel of industry experts will explore how artificial intelligence is transforming design and verification and where standards can help accelerate innovation.

As always, Accellera's success depends on the active participation of our members and the broader engineering community. Whether by contributing to a working group, providing feedback during public reviews, participating in conference discussions, or sharing your expertise, your involvement helps shape the future of our industry.

I look forward to seeing many of you at DAC and at our DVCon conferences around the globe.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

Recent Press Coverage

“Accellera Updates at DVCon U.S. 2026”—SemiWiki, March

In a conversation with Bernard Murphy at DVCon U.S. 2026, Accellera Chair Lu Dai discussed Accellera’s continued growth, expanding global conference presence, and new initiatives including the first SystemC Sprint and the evolution of the Summer of Code program.

The interview also highlights the recently released Clock and Reset Domain Crossing (CDC/RDC) Standard 1.0 and why broader industry adoption now depends on user demand. Lu shared his perspectives with Bernard on trust, intellectual property considerations in AI-assisted standards development, and lessons learned from security incidents in open-source software. Read the full interview for insights into Accellera's latest activities and the future of standards-driven innovation.

 

Functional Safety Language Draft Standard Available Next Week for Public Review!

Accellera’s Functional Safety Language (FSL) standard will be available for public review next week. FSL defines the syntax and semantics of a language and data model for representing and exchanging functional safety intent—focusing on FMEDA—between tools, teams, and operations across the supply chain, from IP to system level.

By enabling automation, interoperability, and traceability, FSL streamlines the implementation of industry standards like ISO 26262 and IEC 61508 for safety-critical systems, significantly increasing confidence in overall safety compliance.

The public review provides an opportunity for the industry to evaluate the specification and provide feedback before it is finalized. The Functional Safety Working Group invites comments and feedback via its Community Forum. Visit Accellera’s Drafts Under Public Review page next week to download the draft.

For more information on the upcoming standard, visit the Functional Safety Working Group page.

 

Join Accellera at the 63rd Design Automation Conference!

“Embracing AI for Advanced Design and Verification”
Tuesday, July 28 12:30-1:45
Long Beach Convention Center, Meeting Room 104C

Join Accellera for a dynamic luncheon exploring how artificial intelligence is reshaping the standards landscape for design and verification. As AI and machine learning are increasingly integrated into EDA workflows—from design generation to verification and system-level optimization—new challenges are emerging around interoperability, data exchange, trust, and reproducibility.

Moderated by Mike Gianfagna of SemiWiki, the panel will feature Dr. Jiang Hu, IEEE Fellow and Eric Rubin Professor at Texas A&M University; David Zhi LuoZhang, CEO of Bronco AI; and Simon Davidmann, AI+EDA researcher, who will offer forward-looking perspectives on the evolving role of AI and standards in design and verification. Attendees will also have the opportunity to share their views on where standardization is most needed across industry and academia.

Seating is limited and on a first-come, first-served basis. While signing up does not guarantee a seat, we encourage you to let us know if you are interested so we can send you updates about the luncheon and help us estimate attendance.

Sign up here >

 

Upcoming Events

DVCon U.S. 2027 Invites Extended Abstract Submissions

DVCon U.S. 2027 is inviting engineers, researchers, and practitioners to submit extended abstracts that showcase innovative methodologies, practical applications, and real-world experiences in the design and verification of electronic systems and integrated circuits. The conference is seeking highly technical content that demonstrates how languages, tools, methodologies, standards, AI technologies, and emerging approaches are being applied to address today’s engineering challenges. Suggested topics include functional verification, safety-critical systems, low-power design, machine learning and AI, design and verification reuse, mixed-signal methodologies, hardware/software co-verification, Portable Stimulus applications, and more.

The submission site opens July 15, 2026, and the deadline for extended abstract submissions is September 7, 2026. In addition, DVCon U.S. 2027 welcomes proposals for sponsored workshops and tutorials, offering additional opportunities to share expertise and engage with the design and verification community. All submissions are due by September 7, 2026. The conference will take place March 1–4, 2027, at the Hyatt Regency Santa Clara in Santa Clara, California.

Additional details, including submission guidelines can be found on the DVCon U.S. 2027 website.

DVCon India 2026 Expands to Three Days

Welcome Message from DVCon India 2026 General Chair

Dear Design, Verification and Validation Community,

It is my great pleasure to welcome you to DVCon India 2026, taking place September 1-3, 2026, at Radisson Blu (Marathahalli) in Bengaluru, the vibrant hub of India’s semiconductor and design innovation ecosystem. As General Chair, I am thrilled to invite you to join us for what promises to be our most expansive event yet. Building on the success of previous DVCon editions, we are excited to extend the program to three full days—inspired by the robust agendas of previous years. This allows even more time for papers, discussions and deep dives into cutting-edge topics in design and verification, including AI-driven methodologies, system-level design, hardware-software co-verification, and emerging standards. We are in the final stages of securing IEEE technical sponsorship, underscoring the conference’s commitment to high-quality, peer-reviewed technical content that advances our industry. DVCon India 2026 is your platform to connect, collaborate, and contribute.

Whether you’re a seasoned expert or emerging talent, your participation will make this event unforgettable. Mark your calendars, and let’s drive the future of design and verification together!

Shreya Dasgupta
General Chair, DVCon India 2026

For more information, and to register, visit the DVCon India website.

Advancing Design and Verification at DVCon Japan 2026

Welcome Message from DVCon Japan 2026 General Chair

Dear friends,
DVCon Japan 2026 will be held on September 10, 2026, in Pacifico Yokohama North.

DVCon focuses on solving problems in a wide range of areas such as logic design, architecture study, functional verification, HW/SW co-verification, analog simulation, functional safety compliance, security verification, and application of AI to development flow in semiconductors and systems. It is the premier conference for learning and discussing best practices in the application of IEEE and Accellera standard languages, formats, and methodologies.

DVCon has been held in the U.S. for more than 30 years and has been held in Japan since 2022. We were able to offer a diverse and in-depth program with a variety of paper presentations, tutorial sessions, and exhibits from sponsors and exhibitors. We would like to thank all the audiences, presenters, sponsors, and all those involved.

DVCon Japan 2026 will be held at Pacifico Yokohama North, this year. The morning sessions will consist of general sessions and panel discussions, and the afternoon will be technical sessions including many paper presentations and tutorials. DVCon is a forum for sharing and discussing the latest information in a wide variety of areas including functional verification strategies, SystemVerilog, UVM, UPF, SystemC, PSS, formal verification methodologies, HLS, AMS, IP-XACT, and more, and discussion in a wide variety of fields. It is also a great opportunity to meet and mingle with other attendees, presenters and attendees, sponsors, and Accellera representatives.

We encourage designers, engineers, and managers to attend. We look forward to seeing you there. Finally, I would like to take this opportunity to thank our Gold and Silver Sponsors and Supporters for their support of the event, as well as the Information Processing Society of Japan and IEEE CEDA AJJC for their sponsorship. 

Genichi Tanaka
General Chair, DVCon Japan 2026

DVCon Japan is accepting paper submission proposals through July 10. For more information on the conference, and submission guidelines, visit the DVCon Japan website.

Get Ready for DVCon Europe 2026

DVCon Europe 2026 will take place November 17–18 in Munich, Germany. The conference and exhibition is the leading European conference dedicated to the practical application of design and verification languages, tools, methodologies, standards, and IP for electronic systems and integrated circuits. The conference will feature keynote presentations, technical papers, tutorials, panel discussions, and an exhibition showcasing the latest innovations from across the EDA ecosystem.

The technical program for DVCon Europe 2026 is currently being finalized and will be announced soon. Be sure to visit the DVCon Europe website for program updates, registration information, and the latest conference news.

SystemC Evolution Day 2026: Shaping the Future of SystemC Standards

Join the 11th SystemC Evolution Day on November 19, 2026, co-located with DVCon Europe in Munich, Germany. This full-day technical workshop brings together members of the SystemC community, industry experts, and Accellera Working Groups to explore the evolution of SystemC standards and help shape the future of the SystemC ecosystem.

Through in-depth technical sessions and collaborative discussions, participants will examine current and emerging standardization topics to accelerate their development for inclusion in future Accellera and IEEE standards. SystemC Evolution Day provides a unique, hands-on forum for exchanging ideas, influencing the direction of SystemC, and connecting with the experts driving its evolution. For more information, including updates on the call for contributions, visit systemc.org.

 

New Videos Available!

Learning PSS Video Series

Accellera's “Learning PSS” video series is a 12-part educational course designed to help engineers understand and apply the Portable Stimulus Standard (PSS). Presented by Tom Fitzpatrick, a PSS expert and charter member of the Accellera PSS Working Group, the series builds from core concepts to practical applications. The first three sessions are now available, with nine more to be released over the next two months.

The series begins with an introduction to PSS and the verification reuse and portability challenges it addresses. Session 2 uses a familiar "Hello World" example to introduce PSS fundamentals, including behaviors, constraints, actions, and activity flows for creating multiple valid verification scenarios from a single model. Session 3 explores horizontal and vertical reuse, showing how PSS models can be reused across projects, system levels, and implementation targets such as SystemVerilog and C. Whether you're new to PSS or looking to expand your expertise, this series provides a practical foundation for mastering the standard.

View the videos on Accellera’s YouTube channel.

For more information about PSS, visit the Portable Stimulus Working Group page.

SystemC Fika Videos

Missed the latest SystemC Fika? The presentations and recordings from the April event are now available to watch on demand.

SystemC Fikas are a series of informal online workshops where the community comes together to discuss the latest developments, applications, and innovations in SystemC. The workshops take their name from the Swedish tradition of fika—taking a break to share coffee and conversation—reflecting the collaborative spirit of the SystemC community.

View the latest SystemC Fika presentations and recordings.

To learn more about SystemC and stay informed about upcoming Fika sessions and other events, visit the SystemC Community Portal.

 

More Resources

Explore Hundreds of Accellera and DVCon Videos On-Demand

Find the latest videos from our working groups, industry events, and technical presentations on Accellera’s YouTube channel. We also host an extensive collection of videos on our Vimeo channel. Check out both platforms and explore content that interests you.

For more videos from our DVCon conferences, visit the DVCon Papers, Posters, Presentations and Video Archive site.

IEEE GET Program – Download Standards at No Cost

The IEEE GET Program provides engineers and chip designers worldwide with no cost access to electronic design and verification standards. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

Accellera Global Sponsors

Contact us if you are interested in becoming a Global Sponsor.

 

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